To reduce the size of Complementary Metal Oxide Semiconductor (CMOS) image sensors, deeply scaled sub-micron CMOS processes are needed. This creates problems, because as the CMOS processes scale to small dimensions, the details of the process integration and structure change, which generally leads to a degradation of pixel performance. Some examples of this degradation relate to shallow trench isolations, and heavily doped retrograde wells. Both are necessary to build deep sub-micron devices, but have adverse effects on dark current for pixels. As a result, much work has been done to re-integrate and re-optimize the photodetector and pixel into new sub-micron CMOS image sensor designs.
Designers face a trade-off with respect to the design and manufacture of sub-micron CMOS devices. On the one hand, not moving to more scaled CMOS processes maintains pixel image quality, but results in relatively large pixels. On the other hand, moving to more scaled CMOS processes produces smaller pixels, but results in low fill factor for these smaller pixels and degradation of image quality. This creates a need to re-integrate and re-design the photodetector to obtain acceptable image quality.
One solution is to build the photodetector separately from the CMOS circuits. The image sensor, for example, can be built on different wafers, and the wafers joined together using three-dimensional integration or wafer-level interconnect technologies. However, image sensor designs that include two different wafers joined together result in an image sensor that has a relatively thick profile with increased complexity, due to the need for inter-wafer connectors between the stacked wafers.